DocumentCode
1001877
Title
Timing Accuracy in Modern ATE
Author
Barber, Mark R. ; Satre, Walter I.
Author_Institution
AT&T Bell Laboratories
Volume
4
Issue
2
fYear
1987
fDate
4/1/1987 12:00:00 AM
Firstpage
22
Lastpage
30
Abstract
LSI test systems built in the 1970s had compact, 60-pin test heads that presented devices under test with open wires leading to lumped-capacitive loads. Today´s VLSI testers have 256-pin test heads with transmission lines leading from the DUTs to driver-comparator circuits that are as far away as 50 cm. Even though these automatic testers are adjusted to subnanosecond accuracy, reflections within the transmission lines can cause timing measurement errors up to 10 ns for MOS devices whose output impedances are not matched to the transmission lines. The authors offer the Advice circuit simulator (an AT&T proprietary version of SPICE) as one way to analyze errors due to transmission line problems before testing. They also discuss ways to correct timing errors. Finally, they recommend that very high speed ICs be designed to drive transmission lines that are terminated with matched resistors at the comparators.
Keywords
Accuracy; Automatic testing; Circuit testing; Distributed parameter circuits; Large scale integration; Reflection; System testing; Timing; Very large scale integration; Wires;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.1987.295102
Filename
4069960
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