Multipurpose Parallelism for VLSI Cad on the RP3

VLSI CAD application developers need the performance of parallel processing in as general a form as possible. The RP3, which is being developed at IBM´s Research Division, provides such generality. Several CAD applications are among the more than 30 applications that have been written in the Epex parallel environment for porting to RP3 when the hardware is complete. Placement by simulated annealing is used here as a significant, deliberately difficult example: its theoretical basis requires serial execution. In the parallel technique used, deviation from the serial algorithm and temporary errors are allowed for more efficient exploitation of parallelism. The result is a convergence rate as good as the original algorithm, with the possibility of efficient execution on hundreds of processors.