• DocumentCode
    1002761
  • Title

    MARS: A Multiprocessor-Based Programmable Accelerator

  • Author

    Agrawal, P. ; Dally, W.J. ; Fischer, W.C. ; Jagadish, H.V. ; Krishnakumar, A.S. ; Tutundjian, R.

  • Author_Institution
    AT&T Bell Laboratories
  • Volume
    4
  • Issue
    5
  • fYear
    1987
  • Firstpage
    28
  • Lastpage
    36
  • Abstract
    MARS, short for microprogrammable accelerator for rapid simulations, is a multiprocessor-based hardware accelerator that can efficiently implement a wide range of computationally complex algorithms. In addition to accelerating many graph-related problem solutions, MARS is ideally suited for performing event-driven simulations of VLSI circuits. Its highly pipelined and parallel architecture yields a performance comparable to that of existing special-purpose hardware simulators. MARS has the added advantage of flexibility because its VLSI processors are custom-designed to be microprogrammable and reconfigurable. When programmed as a logic simulator, MARS should be able to achieve 1 million gate evaluations per second.
  • Keywords
    Acceleration; Circuit simulation; Communication networks; Computational modeling; Computer simulation; Hardware; Logic; Mars; Pipeline processing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.1987.295211
  • Filename
    4070044