• DocumentCode
    1002765
  • Title

    Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL

  • Author

    Wang, Kevin J. ; Swaminathan, Ashok ; Galton, Ian

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of California at San Diego, La Jolla, CA
  • Volume
    43
  • Issue
    12
  • fYear
    2008
  • Firstpage
    2787
  • Lastpage
    2797
  • Abstract
    This paper demonstrates that spurious tones in the output of a fractional-N PLL can be reduced by replacing the DeltaSigma modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms, and presents a phase noise cancelling 2.4 GHz ISM-band CMOS PLL that demonstrates the techniques. The PLL has a 975 kHz loop bandwidth and a 12 MHz reference. Its phase noise has a worst-case reference spur power of - 70 dBc and a worst-case in-band fractional spur power of -64 dBc.
  • Keywords
    CMOS integrated circuits; UHF filters; UHF integrated circuits; delta-sigma modulation; phase locked loops; DeltaSigma modulator; ISM-band CMOS PLL; charge pump offset; digital quantizer; frequency 12 MHz; frequency 2.4 GHz; frequency 975 kHz; loop bandwidth; loop filter; spurious tone suppression techniques; wide-bandwidth fractional-N PLL; worst-case reference spur power; Bandwidth; CMOS technology; Charge pumps; Circuits; Digital filters; Digital modulation; Frequency; Local oscillators; Phase locked loops; Phase noise; Fractional-N phase-locked loop; PLL; frequency synthesis;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2008.2005716
  • Filename
    4684634