Optimum multistage multirate switched capacitor architectures for highly selective interface filtering

Based on the cascade of switched capacitor decimating sections, with optimum implementation and operating with multiple clock rates, a new design methodology is proposed for implementing highly selective filtering functions for analogue-digital interface systems. When compared with more traditional designs, the proposed solution demonstrates remarkable savings both with respect to the capacitance spread and total capacitor area, and the speed at which the operational amplifiers have to operate. Both attributes are paramount for applications where chip size and power consumption are at premium.