DocumentCode :
1002884
Title :
A 90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation of Multimode Optical Fibers at 10 Gb/s
Author :
Agazzi, Oscar E. ; Hueda, Mario R. ; Crivelli, Diego E. ; Carrer, Hugo S. ; Nazemi, Ali ; Luna, Germá N. ; Ramos, Facundo ; López, Ramiro ; Grace, Carl ; Kobeissy, Bilal ; Abidin, Cindra ; Kazemi, Mohammad ; Kargar, Mahyar ; Marquez, César ; Ramprasad, Su
Author_Institution :
ClariPhy Commun. Inc., Irvine, CA
Volume :
43
Issue :
12
fYear :
2008
Firstpage :
2939
Lastpage :
2957
Abstract :
This paper presents the architecture and circuit design of a single chip 32 mm2 90 nm CMOS DSP transceiver for electronic dispersion compensation (EDC) of multimode fibers at 10 Gb/s, based on maximum likelihood sequence detection (MLSD). This is the first MLSD-based transceiver for multimode fibers and the first fully integrated DSP based transceiver for optical channels reported in the technical literature. The digital receiver incorporates equalization, Viterbi detection, channel estimation, timing recovery, and gain control functions. The analog front-end incorporates an 8-way interleaved ADC with self-calibration, a programmable gain amplifier, a phase interpolator, and the transmitter. Also integrated are a XAUI interface, the physical coding sublayer (PCS), and miscellaneous test and control functions. Experimental results using the stressors specified by the IEEE 10 GBASE-LRM standard, as well as industry-defined worst-case fibers are reported. A sensitivity of - 13.68 dBm is demonstrated for the symmetric stressor in a line card application with a 6 inch FR4 interconnect.
Keywords :
CMOS digital integrated circuits; Viterbi detection; channel estimation; digital signal processing chips; equalisers; maximum likelihood sequence estimation; optical fibre dispersion; optical fibre networks; optical interconnections; optical receivers; optical transmitters; CMOS DSP MLSD transceiver; EDC; FR4 interconnect; IEEE 10 GBASE-LRM standard; Viterbi detection; XAUI interface; analog front-end; bit rate 10 Gbit/s; channel estimation; circuit design; digital receiver; electronic dispersion compensation; equalization; fully integrated DSP based transceiver; gain control; integrated AFE; interleaved ADC; line card application; maximum likelihood sequence detection; multimode optical fiber; optical channels; phase interpolator; physical coding sublayer; programmable gain amplifier; size 6 inch; size 90 nm; symmetric stressor; timing recovery; Circuit synthesis; Digital signal processing; Digital signal processing chips; Maximum likelihood detection; Maximum likelihood estimation; Optical fiber dispersion; Optical fibers; Optical receivers; Optical transmitters; Transceivers; DSP; EDC; LRM; MIMO; MLSD; MLSE; MMF; SBVD; SMF; channel estimation; dynamic stressor; equalization; hadamard transform; interleaved ADC; multimode; nonlinear; optical fiber; parallel processing; postcursor stressor; precursor stressor; single-mode; symmetric stressor; volterra kernel;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2008.2006232
Filename :
4684646
Link To Document :
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