Title :
Below 10 ps/gate operation with buried p-layer SAINT FETs
Author :
Yamasaki, Kazuhiko ; Kato, Nei ; Hirayama, Motoko
Author_Institution :
NTT Atsugi Electrical Communication Laboratory, Atsugi, Japan
Abstract :
GaAs SAINT FETs with a p-layer buried under the active layer have achieved below 10 ps/gate (9.9 ps/gate) operation for the first time in semiconductor devices. The p-layer formed by Be+ implantation is completely depleted by the built-in potential. It has successfully alleviated the short channel effects without increasing parastic capacitance.
Keywords :
III-V semiconductors; field effect transistors; gallium arsenide; ion implantation; 9.9 ps/gate operation; Be+ implantation; Buried p-layer; GaAs SAINT FETs; active layer; semiconductor devices; short channel effects;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19840703
