• DocumentCode
    1003006
  • Title

    Top-Down Layout for Hierarchical Custom Design

  • Author

    Ueda, K. ; Kitazawa, H. ; Adachi, T. ; Harada, L.

  • Author_Institution
    LSI Laboratories, NTT
  • Volume
    4
  • Issue
    6
  • fYear
    1987
  • Firstpage
    22
  • Lastpage
    29
  • Abstract
    Champ, a chip floor-plan program, and Alpha, an automatic cell placement and routing system, provide a method for hierarchical custom VLSI design that is highly automated and completely top-down. The system can handle standard cell blocks as well as macro cells such as RAMs, ROMs, PLAs. Champ consists of initial block placement and block packing Designers can execute initial block placement either manually or automatically using a method based on attractive-repulsive forces. Block packing is performed automatically or interactively through the moving and reshaping of blocks, which is done as the chip boundaries are being shrunk. Following the floor-plan design, Alpha automatically executes cell placement and routing. Using Champ/Alpha, only seven mandays are needed to design a 20,000-gate VLSI layout, using a predesigned standard cell library and predesigned macro cells.
  • Keywords
    Design automation; Integrated circuit interconnections; Laboratories; Large scale integration; Large-scale systems; Read-write memory; Routing; Shape; Very large scale integration; Wiring;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.1987.295214
  • Filename
    4070068