A 46-ns 1-Mbit CMOS SRAM

Author

Shimada, Hiroshi ; Kawashima, Shoichiro ; Itoh, Hideo ; Suzuki, Noriyuki ; Yabu, Takashi

Author_Institution

Fujitsu Ltd., Kawasaki, Japan

Volume

23

Issue

1

fYear

1988

Firstpage

53

Lastpage

58

Abstract

A 1-Mb (128 K*8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8- mu m CMOS process technology. Standby power is 25 mu W, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8*8.5- mu m/sup 2/ cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses alpha -particle-induced soft errors. The chip size is 7.6*12.4 mm/sup 2/.<>

Keywords

CMOS integrated circuits; integrated memory circuits; random-access storage; 0.8 micron; 1 MHz; 1 Mbit; 25 muW; 46 ns; 80 mW; CMOS SRAM; PMOS bit-line DC load; access time; active power; four-block access mode; high-resistivity load cell; memory circuits; soft error suppression; standby power; static RAM; triple-polysilicon layers; CMOS process; CMOS technology; Capacitance; Circuit synthesis; Decoding; Frequency; Power dissipation; Pulse amplifiers; Random access memory; Testing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.256

Filename

256