Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time

Backgate biasing is a promising technique for high speed systems. Leakage can be reduced during standby periods by reverse bias while adequate bias in active mode can balance process and temperature variations. This technique introduces no delay penalty in active mode but slow wake up time results in system performance degradation. In this paper, we demonstrate a circuit that provides fast charging of the backgate through a large MOSFET directly connected to the supply. A circuit based on a mirror delay is used to precisely turn off this MOSFET when the backgate voltage has reached the required bias voltage for active mode operation. A nonlinearity compensation operation is implemented to guarantee precise control of the timing despite a non-constant backgate charging rate during transition due to nonlinear backgate capacitance. A sleep-to-active mode transition on the order of 10 ns is demonstrated in a 90 nm CMOS technology. The accelerator occupies less than 2% of the total chip area, consumes 600 muW during the transitions and does not add any bias current during active and sleep modes.