DocumentCode
1003470
Title
High-speed GaAs SCFL divider
Author
Tamura, A. ; Sakashita, T. ; Uenoyama, T. ; Nishii, K. ; Tambo, T. ; Nagano, K. ; Onuma, T.
Author_Institution
Matsushita Electric Industrial Co. Ltd., Central Research Laboratory, Moriguchi, Japan
Volume
21
Issue
14
fYear
1985
Firstpage
605
Lastpage
606
Abstract
A single-clocked divide-by-four circuit with a maximum operating frequency of 5.2 GHz has been developed. The circuit was fabricated using 1 ¿m-gatelength high-transconductance enhancement-mode GaAs MESFETs with Pt-buried gate structure. The basic building block of the circuit is a source-coupled FET logic (SCFL) master-slave flip-flop with ECL-compatible input and output.
Keywords
III-V semiconductors; Schottky gate field effect transistors; counting circuits; field effect integrated circuits; flip-flops; frequency dividers; gallium arsenide; integrated circuit technology; integrated logic circuits; ECL-compatible; GaAs SCFL divider; III-V semiconductors; Pt-buried gate structure; gate length 1 micron; high-transconductance enhancement-mode GaAs MESFETs; master-slave flip-flop; maximum operating frequency of 5.2 GHz; single-clocked divide-by-four circuit; source-coupled FET logic;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19850427
Filename
4250614
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