• DocumentCode
    1003909
  • Title

    Exact computation of maximally dominating faults and its application to n-detection tests for full-scan circuits

  • Author

    Polian, I. ; Pomeranz, I. ; Reddy, S.M. ; Becker, B.

  • Author_Institution
    Albert-Ludwigs-Univ., Freiburg, Germany
  • Volume
    151
  • Issue
    3
  • fYear
    2004
  • fDate
    5/19/2004 12:00:00 AM
  • Firstpage
    235
  • Lastpage
    244
  • Abstract
    The size of an n-detection test set increases approximately linearly with n. This increase in size may be too fast when an upper bound on test set size must be satisfied. A test generation method is proposed for obtaining a more gradual increase in the sizes of n-detection test sets, while still ensuring that every additional test would be useful in improving the test set quality. The method is based on the use of fault-dominance relations to identify a small subset of faults (called maximally dominating faults) whose numbers of detections are likely to have a high impact on the defect coverage of the test set. Structural analysis obtains a superset of the maximally dominating fault set. A method is proposed for determining exact sets of maximally dominating faults. New types of n-detection test sets are based on the approximate and exact sets of maximally dominating faults. The test sets are called (n,n2)-detection test sets and (n,n2,n3)-detection test sets. Experimental results demonstrate the usefulness of these test sets in producing high-quality n-detection test sets for the combinational logic of ISCAS-89 benchmark circuits.
  • Keywords
    hardware-software codesign; logic testing; modems; specification languages; standards; wireless LAN; 5 GHz; FPGA-based prototyping development phase; HDL development phase; HIPERLAN/2 standard; HIPERLAN/2 system; UML-based model; Unified Modelling Language; algorithmic development phase; behavioural model; custom-validation framework; hardware-software design; hardware-software structure; hardware-software validation; instruction-set processor; local area network; modem algorithms; programmable interface unit; wireless LAN modems; wireless communication systems;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2387
  • Type

    jour

  • DOI
    10.1049/ip-cdt:20040141
  • Filename
    1304185