4Mb on-chip-cache bubble memory chips with 4 µm period ion-implanted propagation patterns

4Mb ion-implanted bubble devices (IIBD) with on-chip-cache organization (OCCO) have been designed for 1μm bubbles, and characterized for all functional elements in the devices. The 4Mb memory chip with 9.5×11.8 mm chip size consists of the same two 2Mb units, each of which is divided into 1Mb even and odd sites with 300 strorage loops (s-loops) and cache loops (c-loops), whose bit lengths are 4160 bits and 130 bits, repectively. Basic bit cell size is 4 × 4 μm. The 4Mb chip has an OCCO structure with the following distinguishing functional elements: (1) Bidirectional N-shape transfer gates. (2) A major line replicator with 2 crossed hairpin conductors. (3) DRO detector with folded thin NiFe elements. (4) A hairpin nucleation generator in a 240° super track. (5) Even bit minor loops. Operating margins for the 4Mb IIBD fabricated on (YSmLuBiCa)3(FeGe)5O12are well balanced in all functional elements, and obtained as 25 Oe, sufficient for practical use. It has been found that in-plane holding field applied to stop/start (s/s) direction is necessary for s/s stabilization, and that anisotropy along pattern edges due to stress relief acts a significant role for bit instability and for c-s gate operation. LPE film thickness has been optimized as 1.1 μm for 100-120 keV He+ implantation.