Title :
Computer simulation of an oxide walled emitter STL gate
Author :
Roulston, D.J. ; Depey, M.
Author_Institution :
University of Waterloo, Electrical Engineering Department, Waterloo, Canada
Abstract :
A Schottky transistor logic (STL) gate is studied using computer simulation. The relation between propagation delay time and the spacing between the diffused emitter and the isolation oxide is shown to be such that an optimum spacing exists.
Keywords :
bipolar integrated circuits; digital simulation; integrated logic circuits; logic gates; STL gate; Schottky transistor logic; computer simulation; diffused emitter; isolation oxide; propagation delay;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19830015
