Clockless circuits and system synthesis

Future embedded systems and systems-on-chip are going to be more asynchronous than current VLSI circuits, as predicted by the International Technology Roadmap on Semiconductors. The need for CAD tools for systems without global clocking is rapidly growing. To this end, recent research has been active in two main directions, one being globally asynchronous and locally synchronous systems and the other purely asynchronous or self-timed systems. The state of the art in the synthesis of self-timed circuits from high-level behavioural specifications is reviewed where the two main categories are syntax-driven synthesis and logic-driven synthesis. The primary focus is on the logic-driven approach, where the key role of an intermediate formal model is played by interpretations of Petri nets, such as signal transition graphs. Recent developments in the area of direct mapping and interactive logic synthesis from Petri net specifications are highlighted. A number of logic synthesis tools are compared by means of a simple and widely known example of the greatest common divisor alogrithm.