Low-power system scheduling, synthesis and displays

Many scheduling techniques have been presented recently which exploit dynamic voltage scaling (DVS) and dynamic power management (DPM) for both uniprocessors and distributed systems, as well as both real-time and non-real-time systems. DVS/DPM techniques have been applied not just to processors, but to interconnection networks as well. While such techniques are power-aware and aim at extending battery lifetimes for portable systems, they need to be augmented to make them battery-aware as well. Such power-aware and battery-aware scheduling algorithms are surveyed. Also, system synthesis algorithms for real-time systems-on-a-chip (SoCs), distributed and wireless client-server embedded systems, etc. have begun optimising power consumption in addition to system price. Such algorithms are also surveyed. In many handheld computing devices, it is the display that may consume the largest fraction of system power. Recent work in display-related power optimisation is discussed. Finally, some open problems are pointed out.