Interface state analysis using integrated room temperature gated photoluminescence

A gated room temperature integrated photoluminescence (PL) technique for estimating interface state densities in III-V metal-insultaor-semiconductor (MIS) structures is described. The use of gated low temperature spectral PL has already been demonstrated to be more sensitive than conventional 1 MHz capacitance-voltage (C-V) measurements. Room temperature integrated PL was measured on InP MIS structures and interface state densities of approximately 10¹² (cm² eV)^-1 were calculated, similar to those reported earlier. Furthermore, the elimination of spectroscopic and cryogenic equipment makes this technique simpler and more cost effective than the spectral method, more comparable to C-V measurements.