Maximizing the hash function of authentication codes

A design approach to create small-sized, high-speed implementations of the keyed-hash message authentication code (HMAC) is the focus of this article. The approach showed that the critical path can be further reduced by exploiting special properties of the included hash functions. A significant design effort was made to keep the area low. The experimental results showed that a negligible area penalty was introduce for achieving an increase in throughput up to 390% compared to the competing implementations. Finally, the design was fully tested and verified for the Xilinx Virtex-E FPGA family using a prototype board.