DocumentCode :
1007676
Title :
Designing and implementing an architecture with boundary scan
Author :
van Riessen, R.P. ; Kerkhoff, H.G. ; Kloppenburg, A.
Author_Institution :
Twente Univ., Enschede, Netherlands
Volume :
7
Issue :
1
fYear :
1990
Firstpage :
9
Lastpage :
19
Abstract :
A description is given of a standardized structured test methodology based on the boundary-scan proposal from the Joint Test Action Group (JTAG), which is now IEEE proposed standard P1149.1. Boundary scan does not address testability at the IC level, primarily because there is no standard for designing built-in self-testing (BIST) circuits. An architecture called the hierarchical testable, or H-testable, architecture that is compatible with the JTAG boundary-scan standard for PCB testing and provides BIST at the IC level is presented. The two have been merged, ensuring testability of the hardware from the printed-circuit-board level down to integrated-circuit level. In addition, the architecture has built-in self-test at the IC level. The authors have implemented this design using a self-test compiler.<>
Keywords :
automatic test equipment; integrated circuit testing; printed circuit testing; standards; BIST; IC level; IEEE proposed standard P1149.1; JTAG boundary-scan standard; Joint Test Action Group; PCB testing; built-in self-testing; circuits; integrated-circuit; printed-circuit-board; self-test compiler; structured test methodology; testability; Automatic testing; Built-in self-test; Circuit testing; Computer architecture; Hardware; Integrated circuit testing; Proposals; Registers; Semiconductor device testing; System testing;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/54.46889
Filename :
46889
Link To Document :
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