Graph-theoretic techniques for computer intraconnection minimization

Author

Carothers, Jo Dale ; Cragon, Harvey G.

Author_Institution

Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA

Volume

23

Issue

3

fYear

1993

Firstpage

876

Lastpage

888

Abstract

The design and minimization of computer intraconnections have a great influence on system characteristics such as cost, performance, failure rate, and in the case of VLSI, chip area. The problem addressed was the minimization of computer intraconnections with bandwidth and delay constraints imposed. This research problem has been formally defined as a graph theory problem. An heuristic algorithm, H-RASP2, is presented which approximates a minimal solution for this NP-complete problem in polynomial time. H-RASP2 was tested using a variety of graph sizes and fill´s. Analysis of the results shows that for the test cases H-RASP2 provides an excellent approximation to a minimal solution

Keywords

circuit layout; computational complexity; graph theory; heuristic programming; H-RASP2 algorithm; NP-complete problem; VLSI chip area; bandwidth constraints; computer intraconnection minimization; cost; delay constraints; failure rate; graph-theoretic techniques; heuristic algorithm; performance; polynomial time; Application software; Bandwidth; Costs; Delay; Graph theory; Heuristic algorithms; NP-complete problem; Polynomials; Testing; Very large scale integration;

fLanguage

English

Journal_Title

Systems, Man and Cybernetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9472

Type

jour

DOI

10.1109/21.256559

Filename

256559