Digital Logic Simulation in a Time-Based, Table-Driven Environment

This paper is the first part of a two part sequence describing techniques and implementations for table-driven, time-based, parallel fault simulators for digital logic, Part 1 considers design verification simulation and Part 2 considers parallel fault simulation The major objective of these papers is to introduce basic simulation concepts and developmental considerations and to describe the storage and manipulation of data for these simulation environments. These aspects, from both a theoretical and practical viewpoint, represent the most critical considerations for both accurate and efficient digital logic simulation An adequate coverage of these topics will provide a basic understanding of the underlying consideration, both theoretical and practical, involved in the development of this type of simulator.