A dense voltage-mode Josephson memory cell insensitive to systematic variations in critical current density

A destructive read-out (DRO) memory cell using three Josephson junctions has been devised whose operation depends only on the ratio of critical currents and application of the proper read/write voltages. The effects of run-to-run and across-the-wafer variations in Icare minimized since all three junctions for a given cell are quite close to each other. Additional advantages are: immunity from flux trapping, high circuit density, and fast switching. Since destructive read-out is generally undesirable, a self-rewriting scheme is necessary. Rows and columns of cells with drivers and sense circuits, as well as small memory arrays and decoders have been simulated on SPICE. Power dissipation of cells and bias circuits for a 1K-bit RAM is estimated at about 2 mW. Inclusion of peripheral circuitry raises this by as much as a factor of five depending on the driving scheme and speed desired. Estimated access time is appreciably less than a nanosecond. Preliminary experimental investigations are reported.