A 30 MHz FASTBUS transient digitizer data compactor using CMOS gate arrays

Author

Daviel, A.

Author_Institution

TRIUMF, Vancouver, BC, Canada

Volume

40

Issue

4

fYear

1993

fDate

8/1/1993 12:00:00 AM

Firstpage

780

Lastpage

783

Abstract

A 16-channel data compactor for the BNL 787 experiment is described. The module is designed to compact data from a 16-channel 256-bin 500-MHz charge coupled device (CCD) transient digitizer. Each channel accepts 8-b digitized data from a CCD module, performs pedestal subtraction and spike and zero-suppression, and formats the data together with channel identifiers into 32-b words for readout by FASTBUS. Data compaction is performed on-the-fly at a 30-MHz rate, with a 600-ns initial delay. Data for all channels may be read out in one FASTBUS block transfer operation. The module incorporates a fully featured FASTBUS slave interface built using a CMOS gate array (the PCL) and two bipolar gate arrays (ADIs)

Keywords

CMOS integrated circuits; nuclear electronics; system buses; 16-channel data compactor; 500 MHz; 600 ns; BNL 787 experiment; CCD transient digitizer; CMOS gate arrays; FASTBUS; FASTBUS slave interface; bipolar gate arrays; delay time; pedestal subtraction; Charge coupled devices; Clocks; Compaction; Councils; Fastbus; Field programmable gate arrays; Light emitting diodes; Monitoring; Programmable logic arrays; Prototypes;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.256660

Filename

256660