Title :
New test structure for VLSI self-test: the structured test register (STR)
Author :
Paraskeva, M. ; Knight, W.L. ; Burrows, D.F.
Author_Institution :
Plessey ESR Limited, Romsey, UK
Abstract :
A new test structure which facilitates self-test in digital VLSI integrated circuits is presented. This test structure, termed the structured test register (STR), is constructed by adding some extra components to an otherwise standard BILBO. The advantages of this circuit in terms of increased fault coverage on both the functional and self-test parts of the circuit are described.
Keywords :
VLSI; automatic testing; digital integrated circuits; logic testing; VLSI self-test; digital VLSI; fault coverage; structured test register; test structure;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19850604
