Title :
An adaptive timing-driven placement for high performance VLSIs
Author :
Sutanthavibul, Suphachai ; Shragowitz, Eugene ; Lin, Rung-Bin
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fDate :
10/1/1993 12:00:00 AM
Abstract :
An application of constructive successive augmentation methodology to VLSI placement under constraints on routability, area and timing is described. To improve effectiveness of decision making, the placement algorithm uses adaptive and look-ahead procedures. This methodology was implemented in the placer-router JUNE for macrocell-library-based sea-of-gates design style with over-the-cell routing. JUNE achieves high utilization of area and timing requirements for real-life designs
Keywords :
VLSI; circuit layout CAD; logic CAD; logic arrays; network routing; JUNE placer-router; VLSIs; adaptive timing-driven placement; area; constructive successive augmentation methodology; look-ahead procedures; macrocell-library-based sea-of-gates design style; over-the-cell routing; real-life designs; routability; Circuits; Clocks; Decision making; Delay; Particle separators; Routing; Timing; Upper bound; Very large scale integration; Wire;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
