An adaptive timing-driven placement for high performance VLSIs

Author

Sutanthavibul, Suphachai ; Shragowitz, Eugene ; Lin, Rung-Bin

Author_Institution

Intel Corp., Hillsboro, OR, USA

Volume

Issue

fYear

1993

fDate

10/1/1993 12:00:00 AM

Firstpage

1488

Lastpage

1498

Abstract

An application of constructive successive augmentation methodology to VLSI placement under constraints on routability, area and timing is described. To improve effectiveness of decision making, the placement algorithm uses adaptive and look-ahead procedures. This methodology was implemented in the placer-router JUNE for macrocell-library-based sea-of-gates design style with over-the-cell routing. JUNE achieves high utilization of area and timing requirements for real-life designs

Keywords

VLSI; circuit layout CAD; logic CAD; logic arrays; network routing; JUNE placer-router; VLSIs; adaptive timing-driven placement; area; constructive successive augmentation methodology; look-ahead procedures; macrocell-library-based sea-of-gates design style; over-the-cell routing; real-life designs; routability; Circuits; Clocks; Decision making; Delay; Particle separators; Routing; Timing; Upper bound; Very large scale integration; Wire;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.256922

Filename

256922

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1010972