Modeling of the charge balance condition on floating gates and simulation of EEPROMs

Author

Chen, Datong ; Sugino, Satoshi ; Yu, Zhiping ; Dutton, Robert W.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

12

Issue

10

fYear

1993

fDate

10/1/1993 12:00:00 AM

Firstpage

1499

Lastpage

1502

Abstract

A robust numerical model for the charge balance condition (CBC) on floating gates (FG) is presented, in which the quasi-Fermi level, instead of the potential (as in conventional models), is assumed to be a constant in the FG. By solving Poisson´s equation in the FG region with an extra equation for the CBC, the accurate distribution of both potential and charge can be obtained. A quasi-stationary scheme is developed to simulate the writing or erasing procedure of EEPROM cells, which may serve as a useful tool for accurate simulation of devices such as EEPROMs or EPROMs. Simulation results reveal a significant degradation of tunneling efficiency when N_FG<10²⁰ cm^-3, which is improperly ignored in the flat-potential model

Keywords

EPROM; MOS integrated circuits; insulated gate field effect transistors; integrated memory circuits; semiconductor device models; EEPROMs; Poisson´s equation; charge balance condition; degradation; erasing procedure; flat-potential model; floating gates; quasi-Fermi level; quasi-stationary scheme; robust numerical model; tunneling efficiency; writing procedure; Capacitance; Charge carrier processes; Degradation; Doping; EPROM; Numerical models; Poisson equations; Robustness; Tunneling; Writing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.256923

Filename

256923