Implementing Decay Techniques using 4T Quasi-Static Memory Cells

This paper proposes the use of four-transistor (4T) cacheand branch predictor array cell designs to address increasingworries regarding leakage power dissipation. While 4T designslose state when infrequently accessed, they have very lowleakage, smaller area, and no capacitive loads to switch. Thisshort paper gives an overview of 4T implementation issues anda preliminary evaluation of leakage-energy savings that showsimprovements of 60-80%