DocumentCode
1011991
Title
In-network cache coherence
Author
Eisley, Noel ; Peh, Li-Shiuan ; Shang, Li
Author_Institution
Dept. of Electr. Eng., Princeton Univ., NJ
Volume
5
Issue
1
fYear
2006
Firstpage
34
Lastpage
37
Abstract
We propose implementing cache coherence protocols within the network, demonstrating how an in-network implementation of the MSI directory-based protocol allows for in-transit optimizations of read and write delay. Our results show 15% and 24% savings on average in memory access latency for SPLASH-2 parallel benchmarks running on a 4times4 and a 16times16 multiprocessor respectively
Keywords
benchmark testing; cache storage; delays; memory architecture; memory protocols; parallel processing; MSI directory-based protocol; SPLASH-2 parallel benchmarks; memory access latency; network cache coherence protocols; read delay; write delay; Access protocols; Coherence; Delay; Fabrics; Memory architecture; Moore´s Law; Multiprocessor interconnection networks; Notice of Violation; cache coherence; interconnection network;
fLanguage
English
Journal_Title
Computer Architecture Letters
Publisher
ieee
ISSN
1556-6056
Type
jour
DOI
10.1109/L-CA.2006.9
Filename
1650141
Link To Document