• DocumentCode
    1012464
  • Title

    Threshold voltage adjustable process for self-aligned gate GaAs JFET

  • Author

    Tiku, S.K.

  • Author_Institution
    Texas Instruments Inc., Central Research Laboratories, Dallas, USA
  • Volume
    21
  • Issue
    23
  • fYear
    1985
  • Firstpage
    1091
  • Lastpage
    1093
  • Abstract
    A self-aligned GaAs JFET process, allowing threshold voltage adjustment after gate metallisation, has been developed. Zn-doped tungsten silicide was used as the gate metallisation, which also acts as the source of Zn diffusion for the p-junction gate. The threshold voltage was adjusted by repeated short thermal pulses in a lamp annealer at 550°C. The process has the potential to solve the most difficult task of threshold voltage control necessary for achieving high yield in LSI fabrication.
  • Keywords
    III-V semiconductors; gallium arsenide; junction gate field effect transistors; large scale integration; semiconductor junctions; GaAs JFET; LSI fabrication; WSi2:Zn; Zn diffusion; gate metallisation; lamp annealer; p-junction gate; self-aligned gate; threshold voltage adjustable process; threshold voltage control;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19850775
  • Filename
    4251617
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1012464