• DocumentCode
    1012545
  • Title

    Comments on "Ternary scan design for VLSI testability" by M. Hu and K.C. Smith

  • Author

    Molyneaux, Robert F. ; Albicki, Alexander

  • Author_Institution
    Dept. of Electr. Eng., Rochester Univ., NY, USA
  • Volume
    38
  • Issue
    2
  • fYear
    1989
  • Firstpage
    256
  • Lastpage
    263
  • Abstract
    An alternative design is found to be significantly faster than the one proposed by Hu and Smith (see ibid., vol.C-53, p.167-170, (1986)). The performance of the alternative is compared to the original. A means to buffer the signal is presented and its performance is reported. An estimate of silicon area saved versus area spent is made.<>
  • Keywords
    VLSI; logic design; logic testing; ternary logic; VLSI testability; silicon area; ternary scan design; Silicon; Testing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.16502
  • Filename
    16502
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1012545