Title :
Comments on "Ternary scan design for VLSI testability" by M. Hu and K.C. Smith
Author :
Molyneaux, Robert F. ; Albicki, Alexander
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
Abstract :
An alternative design is found to be significantly faster than the one proposed by Hu and Smith (see ibid., vol.C-53, p.167-170, (1986)). The performance of the alternative is compared to the original. A means to buffer the signal is presented and its performance is reported. An estimate of silicon area saved versus area spent is made.<>
Keywords :
VLSI; logic design; logic testing; ternary logic; VLSI testability; silicon area; ternary scan design; Silicon; Testing; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
