Title :
0.25 micrometre smart power technology optimised for wireless and consumer applications
Author :
Zhu, R. ; Parthasarathy, V. ; Khemka, V. ; Bose, A. ; Roggenbauer, T. ; Lee, G. ; Baumert, B. ; Hui, P. ; Rodriquez, P. ; Collins, D.
Author_Institution :
SPS, Motorola Inc., Tempe, AZ, USA
fDate :
6/17/2004 12:00:00 AM
Abstract :
In this paper, simultaneous optimisation of 4.5-5.5 V N and PMOS devices, 20-30 V NLDMOS, and NPN and PNP bipolar devices in a 0.25 μm smart power technology for portable wireless and consumer applications is discussed. With the addition of two designated wells, ultra-low resistance N and PMOS devices with good analogue characteristics, best in class 30 V NLDMOS, and integrated high performance NPN and PNP bipolar devices are demonstrated. Practical implementation of a high voltage, isolated diode using an existing device is also discussed and demonstrated.
Keywords :
anodes; electron emission; insulated gate bipolar transistors; 600 V; P-buffer layer; anode design; ion implantations; n-buffer dose; n-buffer layer; p-emitter dose; p-emitter injection efficiency; p-type layer; power loss; punch through insulated gate bipolar transistor; tail current; tail loss; thin wafer PT-IGBT; transparent P-emitter; turn-off waveforms oscillation;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
DOI :
10.1049/ip-cds:20040456
