DocumentCode :
1013166
Title :
A high-level approach to test generation
Author :
Narain, P. ; Saab, Daniel G. ; Kunda, Ramchandra P. ; Abraham, Jacob A.
Author_Institution :
IBM Corp., Endicott, NY, USA
Volume :
40
Issue :
7
fYear :
1993
fDate :
7/1/1993 12:00:00 AM
Firstpage :
483
Lastpage :
492
Abstract :
A high-level test generation algorithm based upon the branch and bound search procedure is presented. The algorithm is described in detail, highlighting the various tradeoffs that are involved. A complete dependency-directed backtracking scheme that has significant advantage over chronological backtracking is introduced. Different uses for the algorithm are presented to show its versatility. Results showing significant performance improvement over gate level test generation are also presented. The ability to generate tests for incomplete designs is a major strength of this scheme
Keywords :
fault location; logic testing; search problems; branch/bound search procedure; dependency-directed backtracking scheme; digital circuit testing; high-level test generation algorithm; incomplete designs; logic faults; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Digital circuits; Flow graphs; Helium; Jacobian matrices; Production; Test pattern generators;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7122
Type :
jour
DOI :
10.1109/81.257304
Filename :
257304
Link To Document :
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