High-level transistor operation and transport capacitance

A two-dimensional analysis of high-level transistor operation is presented which includes the effects of an extended base region, internal emitter biasing, γ-falloff, unequal collector and emitter dimensions, and surface recombination. The transistor model considered is directly appropriate to the strip-type geometry, but also yields results which are approximately valid for the ring-and dot-type structures under certain conditions. Transforming the geometry permits a solution to be obtained for the charge-density distribution in the base as well as the current density distribution at the emitter and collector junctions. From these relations, both the collector and emitter transport (diffusion) capacitances are also determined. Two complete numerical evaluations of the theoretical results are given, first for a symmetrical unit with equal emitter and collector dimensions, and second for an unsymmetrical unit with the collector dimension 24 per cent greater than that of the emitter. It is indicated that an appreciable fraction of the total base charge can exist external to the emitter and collector, particularly for very high-level operation, causing large increases (1.5 to 3 times the one-dimensional values) in both the emitter and collector transport capacitances, particularly for units having grossly extended base regions and low surface-recombination velocities. Further shown is the effect of increasing the collector dimension over that of the emitter; the capacitances are appreciably lowered and the transport efficiency (and thus the current gains) is increased. Finally, some collector transport capacitance measurements are presented covering the entire operating range which tend to substantiate the theoretical results.