DocumentCode :
1013643
Title :
Concurrent Error Detection in Reed–Solomon Encoders and Decoders
Author :
Cardarilli, G.C. ; Pontarelli, S. ; Re, M. ; Salsano, A.
Author_Institution :
Rome Univ. "Tor Vergata", Rome
Volume :
15
Issue :
7
fYear :
2007
fDate :
7/1/2007 12:00:00 AM
Firstpage :
842
Lastpage :
846
Abstract :
Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2m). These properties are related to the parity of the binary representation of the elements of the Galois field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.
Keywords :
Galois fields; Reed-Solomon codes; arithmetic codes; decoding; error correction codes; error detection codes; fault tolerance; logic circuits; logic design; RS codes; arithmetic operations; binary representation; concurrent error detection; fault tolerance; self-checking Reed-Solomon decoder architecture; self-checking Reed-Solomon encoder architecture; Arithmetic; Circuit faults; Decoding; Delay; Error correction codes; Fault detection; Fault tolerance; Galois fields; Polynomials; Redundancy; Error correction coding; Reed–Solomon codes; fault tolerance;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2007.899241
Filename :
4252114
Link To Document :
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