Title :
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design
Author :
Lin, Shih-Ping ; Lee, Chung-Len ; Chen, Jwu-E ; Chen, Ji-Jan ; Luo, Kun-Lun ; Wu, Wen-Ching
Author_Institution :
Nat. Chiao Tung Univ., Hsinchu
fDate :
7/1/2007 12:00:00 AM
Abstract :
The random-like filling strategy pursuing high compression for today´s popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. The scheme utilizes a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied automatic test pattern generation (ATPG)-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with only a small area design overhead.
Keywords :
automatic test pattern generation; circuit testing; data compression; automatic test pattern generation; circuit testing; decoding buffer; low-power testing; multilayer data copy test data compression; multiple scan design; shifting-in power reduction; test power reduction; Automatic test pattern generation; Automatic testing; Circuit testing; Costs; Nonhomogeneous media; Power generation; System testing; System-on-a-chip; Test data compression; Test pattern generators; Circuit testing; low-power testing; test data compression; test pattern generation;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2007.899232