CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation

A specific 0.5 μm CMOS/SIMOX technology was developed for a gate array/sea of gate (SOG) using field-shield (FS) isolation to overcome a pending problem of source-to-drain breakdown voltage (BV_ds) lowering. FS isolation is capable of improving BV_ds because surplus holes generated by impact ionization at the drain region are collected through the body region under the FS gate. BV_ds was maintained at a level of junction breakdown before reaching the punchthrough limitation at a gate length of around 0.3 μm using the FS isolation. The FS isolation technique was successfully applied to an SOG gate array on a SIMOX substrate. The gate array has the same area as that on the bulk-Si and is compatible to a conventional bulk-Si CAD system because the layout is basically the same. A 53-stage ring oscillator fabricated on the FS isolated SOG gate array exhibited 1.7 times higher speed operation than that on a bulk-Si counterpart, keeping low power consumption characteristics up to a drain voltage of 3 V