Title :
A Novel Five-Photo-Mask Low-Temperature Polycrystalline-Silicon CMOS Structure With Improved Contact Resistance
Author :
Lee, Seok-Woo ; Park, Soo-Jeong ; Kim, Sung Ki ; Baek, Myoung Kee ; Lim, Kyoung Moon ; Park, Yong In ; Kim, Chang-Dong ; Kang, In Byeong
Author_Institution :
LG Display R&D Center, Paju
Abstract :
In this letter, a novel five-mask low-temperature polycrystalline-silicon (LTPS) complementary metal-oxide-semiconductor (CMOS) structure was proposed to improve cost competitiveness of CMOS products on the market and was verified by manufacturing test samples using the five-mask LTPS CMOS process. Selective contact-barrier-metal formation process was first introduced to solve the high-contact-resistance problem encountered between indium-tin-oxide and doped poly-Si source/drain. The five-mask CMOS devices showed comparable device performances to CMOS devices with conventional structure, i.e., 1.32 V of threshold voltage and 267.6 cm2/Vmiddots of maximum field-effect mobility for NMOS, and those of -1.24 V and 125.2 cm2/Vmiddots for PMOS, respectively.
Keywords :
CMOS integrated circuits; contact resistance; elemental semiconductors; indium compounds; low-temperature techniques; masks; silicon; ITO-Si; NMOS field-effect mobility; PMOS; complementary metal-oxide-semiconductor structure; contact resistance; five-photo-mask LTPS CMOS process; low-temperature polycrystalline-silicon; selective contact-barrier-metal formation process; voltage 1.32 V; Active-matrix liquid-crystal display (AMLCD); complementary metal–oxide–semiconductor (CMOS); complementary metal–oxide–semiconductor (CMOS); contact resistance; low-temperature polycrystalline silicon (LTPS); thin-film transistor (TFT);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2008.2008451
