Title :
A real experience on configuring a wafer scale 2D array of monobit processors
Author :
Boubekeur, Ahmed ; Patry, Jean Luc ; Slimane-kadi, Mustapha ; Saucier, Gabriele ; Trilhe, Jacques
Author_Institution :
Inst. Nat. Polytech. de Grenoble, France
fDate :
11/1/1993 12:00:00 AM
Abstract :
Presents hardware and software techniques for configuring a wafer scale 2D array. A switching network independent of the processing elements (PEs) has been designed and implemented. Two algorithms find and program an optimized target array in a reversible or irreversible manner. This paper is based on a wafer scale design for low-level image processing
Keywords :
VLSI; digital signal processing chips; image processing equipment; parallel architectures; hardware techniques; irreversible manner; low-level image processing; monobit processors; optimized target array; processing elements; reversible manner; software techniques; switching network; wafer scale 2D array; Hardware; Helium; Image processing; Multiplexing; Pixel; Proposals; Registers; Switches; Testing; Wafer scale integration;
Journal_Title :
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
