Title :
Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI Technology
Author :
Kim, Daeik ; Kim, Jonghae ; Plouchart, Jean-Olivier ; Cho, Choongyeun ; Trzcinski, Robert ; Kumar, Mahender ; Norris, Christine
Author_Institution :
IBM Semicond. Res. and Dev. Center, Hopewell Junction
fDate :
7/1/2007 12:00:00 AM
Abstract :
This letter presents symmetric vertical parallel plate (VPP) capacitors in 65-nm silicon-on-insulator CMOS technology. Three VPP capacitors with different metal layer options are examined with respect to effective capacitance density and -factor. An effective capacitance of 2.18 and a -factor of 23.2 at 1 GHz are obtained from a 1x + 2x (M1-M6) metal layer configuration´s pre-de-embedding measurement. VPP capacitor symmetry, mismatch, leakage current density, vertical scalability, and variation characteristics from a 300-mm wafer are discussed.
Keywords :
CMOS integrated circuits; UHF integrated circuits; capacitors; silicon-on-insulator; CMOS technology; SOI technology; frequency 1 GHz; horizontal scalability; on-chip RF circuits; radio frequency passive component; silicon-on-insulator; size 300 mm; size 65 nm; symmetric vertical parallel plate capacitor; vertical native back-end-of-line capacitor; vertical scalabilit; CMOS technology; Capacitance; Capacitors; Circuits; Leakage current; Manufacturing; Radio frequency; Scalability; Silicon on insulator technology; Substrates; 65-nm silicon-on-insulator (SOI) CMOS technology; Radio frequency (RF) passive component; vertical and horizontal scalability; vertical native back-end-of-line (BEOL) capacitor; vertical parallel plate (VPP) capacitor;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2007.899464
