Title :
A Digital PLL With a Stochastic Time-to-Digital Converter
Author :
Kratyuk, Volodymyr ; Hanumolu, Pavan Kumar ; Ok, Kerem ; Moon, Un-Ku ; Mayaram, Kartikeya
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
Abstract :
A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution. A prototype DPLL test chip has been fabricated in a 0.13-mum CMOS process, features a 0.7-1.7-GHz oscillator tuning range and a 6.9-ps rms jitter, and consumes 17 mW under 1.2-V supply while operating at 1.2 GHz.
Keywords :
CMOS digital integrated circuits; UHF integrated circuits; UHF oscillators; convertors; digital phase locked loops; field effect MMIC; integrated circuit noise; jitter; CMOS process; dual-loop digital phase-locked loop; frequency 0.7 GHz to 1.7 GHz; high-frequency delta-sigma dithering; jitter; latches; oscillator; power 17 mW; size 0.13 mum; stochastic time-to-digital converter; voltage 1.2 V; Digital phase-locked loop (DPLL); digitally controlled oscillator (DCO); stochastic time-to-digital converter (STDC);
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2008.2010109
