Title :
Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination
Author :
Chen, Zhengang ; Brandon, Tyler L. ; Bates, Stephen ; Elliott, Duncan G. ; Cockburn, Bruce F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB
Abstract :
Low-density parity-check convolutional codes (LDPC-CCs) have demonstrated comparable error-correcting performance to LDPC block codes (LDPC-BCs). However, the LDPC-CC encoder requires termination when applied to finite-length data frames to ensure that the trailing information bits are fully protected. In this paper, the LDPC-CC encoder design is investigated, and a novel termination scheme is proposed. Starting from any encoder state, the proposed scheme is capable of generating a termination sequence in hardware without padding, thus minimizing the rate loss due to termination. A high-speed architecture for LDPC-CC encoders with built-in termination is proposed. Synthesis results for LDPC-CCs of code memory size up to 512 demonstrate maximum encoding throughputs of around 1 Gb/s for a 90-nm CMOS technology. The implementation cost for such encoders is shown to be reasonably low for average-sized LDPC-CCs.
Keywords :
convolutional codes; parity check codes; CMOS technology; LDPC codes; encoding throughputs; error-correcting performance; finite-length data frames; low-density parity-check convolutional code encoders; termination; Application specific integrated circuits; Block codes; CMOS technology; Convolutional codes; Decoding; Encoding; Hardware; High speed integrated circuits; Parity check codes; Sparse matrices; Application-specific integrated circuits (ASICs); convolutional codes; error correction coding; high-speed integrated circuits; low-density parity-check (LDPC) codes; trellis termination;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2008.925813