DocumentCode :
1014854
Title :
Placement constraints in floorplan design
Author :
Young, Evangeline F Y ; Chu, Chris C N ; Ho, M.L.
Author_Institution :
Dept. of Comput. Sci. & Eng., The Chinese Univ. of Hong Kong, China
Volume :
12
Issue :
7
fYear :
2004
fDate :
7/1/2004 12:00:00 AM
Firstpage :
735
Lastpage :
745
Abstract :
In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like datapath alignment and I/O connection. There are several previous works focusing on some particular kinds of placement constraints. In this paper, we will present a unified method to handle all of them simultaneously, including preplace constraint, range constraint, boundary constraint, alignment, abutment, and clustering, etc., in general, nonslicing floorplans. We have used incremental updates and an interesting idea of reduced graph to improve the runtime of the method. We tested our method using some benchmark data with about 1/8 of the modules having placement constraints and the results are very promising. Good packings with all the constraints satisfied can be obtained efficiently.
Keywords :
VLSI; benchmark testing; circuit layout CAD; constraint handling; integrated circuit layout; abutment constraint; alignment constraint; benchmark data; boundary constraint; clustering constraint; datapath alignment; floorplan design; nonslicing floorplans; packing constraint; placement constraints; preplace constraint; range constraint; Benchmark testing; Circuit optimization; Computer science; Constraint optimization; Design automation; Design optimization; Integrated circuit interconnections; Routing; Runtime; Very large scale integration;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2004.830915
Filename :
1308208
Link To Document :
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