Title :
Balanced high-speed residue number VLSI multiplier with error detection
Author :
Lo, H.-Y. ; Yang, Ted C.
Author_Institution :
Dept. of Inf. Eng., Feng-Chia Univ., Tai-Chung, Taiwan
fDate :
6/1/1991 12:00:00 AM
Abstract :
A balanced residue number VLSI multiplier is proposed which eliminates the extra delay for an unbalanced residue multiplier. The number of adding stages used in the VLSI multiplier is reduced from three to two. The authors also describe how redundant residue number system (RNS) properties can be used for error detection. These improvements allow a residue multiplier with a 48-72 bit dynamic range, to perform 3.3 M multiplication/s without pipelining or 10 M multiplication/s with pipelining
Keywords :
VLSI; digital arithmetic; error detection; integrated logic circuits; multiplying circuits; pipeline processing; VLSI multiplier; adding stages; balanced multiplier; error detection; high-speed; pipelining; redundant RNS; residue number;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings G
