Title :
Optimal matrix multiplication on fault-tolerant VLSI arrays
Author :
Varman, P.J. ; Ramakrishnan, I.V.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
Abstract :
A fault-tolerant array for matrix multiplication that explicitly incorporates mechanisms for easy testability and reconfigurability is described. All signals in the array travel only a constant distance (independent of array size) in any clock cycle. An optimal-time algorithm, designed for multiplying matrices, is described. The algorithm is an efficient simulation of a 2-D systolic algorithm for multiplying matrices.<>
Keywords :
VLSI; fault tolerant computing; 2-D systolic algorithm; clock cycle; fault-tolerant VLSI arrays; optimal matrix multiplication; optimal-time algorithm; reconfigurability; simulation; testability; Algorithm design and analysis; Clocks; Fault tolerance; Testing; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
