Title :
A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors
Author_Institution :
RMIT Univ., Melbourne
Abstract :
A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed. The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate. Each cell in the array can act as logic or interconnect, or both, contrasting with current field-programmable gate array structures in which logic and interconnect are built and configured separately. Simulation results are presented for a fully depleted SOI DG-MOSFET implementation and contrasted with two other proposals from the literature based on directed self-assembly.
Keywords :
MOSFET; field programmable gate arrays; low-power electronics; reconfigurable architectures; silicon-on-insulator; SOI DG-MOSFET; double-gate transistors; field programmable gate array; low-power reconfigurable logic array; reconfigurable architecture; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic circuits; Logic devices; Nanoscale devices; Power system reliability; Programmable logic arrays; Reconfigurable architectures; Reconfigurable logic; CMOS integrated circuits; double-gate (DG) transistors; logic circuits; nanotechnology; reconfigurable architectures;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2007.912024
