• DocumentCode
    1016443
  • Title

    Circuit Simulation of Threshold-Voltage Degradation in a-Si:H TFTs Fabricated at 175 °C

  • Author

    Shringarpure, Rahul ; Venugopal, Sameer ; Li, Zi ; Clark, Lawrence T. ; Allee, David R. ; Bawolek, Edward ; Toy, Daniel

  • Author_Institution
    Arizona State Univ., Tempe
  • Volume
    54
  • Issue
    7
  • fYear
    2007
  • fDate
    7/1/2007 12:00:00 AM
  • Firstpage
    1781
  • Lastpage
    1783
  • Abstract
    This brief presents a novel approach to modeling gate bias-induced threshold-voltage (Vth) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The Vth degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated Vth shift with measured data in a TFT latch circuit.
  • Keywords
    circuit simulation; silicon; thin film transistors; Si; circuit simulation; display technology; gate bias; hydrogenated amorphous silicon thin-film transistors; latch circuit; temperature 175 C; threshold-voltage degradation; Amorphous silicon; Circuit simulation; Degradation; Displays; Latches; Physics; SPICE; Stress; Temperature; Thin film transistors; Circuit simulation; SPICE; display technology; hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT); threshold-voltage degradation;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2007.899667
  • Filename
    4252383
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1016443