• DocumentCode
    1017149
  • Title

    Reasoning assertionally about real-time systems

  • Author

    Shankar, A. Udaya

  • Author_Institution
    Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
  • Volume
    82
  • Issue
    1
  • fYear
    1994
  • fDate
    1/1/1994 12:00:00 AM
  • Firstpage
    172
  • Lastpage
    183
  • Abstract
    We consider a real-time system defined by a set of programs that execute concurrently on one or more (hardware) processors and interact between themselves and with the environment. We show how to reason assertionally about such real-time systems, using standard (non-real-time) assertional techniques (i.e. Hoare-logic and linear-history temporal logic). The key step is to transform the set of programs to a state transition system, using “epoch variables” to model assumptions on statement execution times, interprocessor communication times, scheduling policy, and allocation of programs to processors. Our method is illustrated on a nontrivial example consisting of three concurrent programs: a sensor that buffers inputs from the environment, an integrator that periodically integrates the buffered inputs into a database, and a query-handler that responds to queries from the environment by accessing the database. We model the system for two different program-to-processor allocations (dedicated processors and shared processors with priority scheduling). We prove that the system satisfies desired properties (e.g. bounded query response time and absence of buffer overflow)
  • Keywords
    formal verification; multiprocessing programs; parallel programming; real-time systems; resource allocation; scheduling; temporal reasoning; Hoare-logic; assertional reasoning; buffer overflow; concurrent programs; epoch variables; interprocessor communication times; linear-history temporal logic; program-to-processor allocations; query-handler; real-time systems; scheduling policy; state transition system; Buffer overflow; Buffer storage; Computer science; Databases; Delay; Hardware; Interference; Logic programming; Processor scheduling; Real time systems;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/5.259434
  • Filename
    259434