Title :
Deep submicrometer super self-aligned Si bipolar technology with 25.4 ps ECL
Author :
Konaka, Shinsuke ; Ugajin, Mamoru ; Matsuda, Tadahito
Author_Institution :
NTT LSI Labs., Kanagawa, Japan
fDate :
1/1/1994 12:00:00 AM
Abstract :
A new deep submicron double-poly self-aligned Si bipolar technology has been developed using a 0.3-μm design rule, a collector polysilicon trench electrode, and oxide-filled trench isolation. This technology is called “High-Performance Super Self-Aligned Process Technology” or HSST. 0.3-μm minimum patterning is achieved by electron-beam direct writing technology. The HSST bipolar transistor is 2.5 times smaller than the previous 1-μm SST-1B. Owing to its horizontal reduction and an fT of 22.3 GHz at Vce=1 V, the ECL gate attains 25.4 ps/G at 1.58 mA, which is a 30% improvement on the SST-1B. By including parasitic capacitances of the base polyelectrode and polyresistors, the ECL delay time is accurately simulated for low-power operation. It is shown that the HSST is a very promising technology for the development of future high-speed communication systems
Keywords :
bipolar integrated circuits; bipolar transistors; electron beam lithography; elemental semiconductors; emitter-coupled logic; integrated circuit technology; silicon; 0.3 micron; 1 V; 1.58 mA; 22.3 GHz; 25.4 ps; ECL; HSST; High-Performance Super Self-Aligned Process Technology; Si; base polyelectrode; bipolar transistor; collector polysilicon trench electrode; deep submicron double-poly self-aligned Si bipolar technology; delay time; electron-beam direct writing technology; high-speed communication systems; horizontal reduction; low-power operation; oxide-filled trench isolation; parasitic capacitances; patterning; polyresistors; submicrometer super self-aligned Si bipolar technology; Bipolar transistors; CMOS technology; Delay effects; Electrodes; Isolation technology; Parasitic capacitance; Silicon carbide; Space technology; Wiring; Writing;
Journal_Title :
Electron Devices, IEEE Transactions on
