A new technique for forming a shallow link base in a double polysilicon bipolar transistor

Author

Hayden, J.D. ; Burnett, J.D. ; Pfiester, J.R. ; Woo, M.P.

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

Volume

41

Issue

1

fYear

1994

fDate

1/1/1994 12:00:00 AM

Firstpage

63

Lastpage

68

Abstract

A new technique is presented for forming a shallow link base in a double polysilicon bipolar transistor. This method is easily integrated into an advanced BiCMOS process, making use of a disposable polysilicon spacer technology for MOSFET LDD formation. This new scheme allows independent optimization of active and link base regions while providing improvements in base-emitter breakdown and resistance to bipolar hot carrier degradation

Keywords

BiCMOS integrated circuits; bipolar transistors; elemental semiconductors; integrated circuit technology; silicon; IC fabrication; MOSFET LDD formation; Si; advanced BiCMOS process; base-emitter breakdown; bipolar hot carrier degradation resistance; disposable polysilicon spacer technology; double polysilicon bipolar transistor; shallow link base; BiCMOS integrated circuits; Bipolar transistors; Boron; CMOS process; Degradation; Electric breakdown; Hot carriers; MOSFET circuits; Random access memory; Space technology;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.259621

Filename

259621