Operation of a VBL memory read/write gate

A read/write gate for a VBL memory, a dual-conductor major line and an interface circuit between the read/write gate and the major line were designed and fabricated on an as-grown garnet wafer supporting 5 µm bubbles. For the "write" operation, the operating margin of the expanding current is between 23 and 48 mA, with 500 to 700 nsec pulse width. For the "read" operation, the operating margin of the expanding current is between 8 and 12 mA, with a 1.5 to 2 µsec pulse width. This gate allowed the stripes to be packed 2 stripe widths apart which makes the maximum storage density in this direction possible.